• DocumentCode
    1171241
  • Title

    Multiterminal net routing for partial crossbar-based multi-FPGA systems

  • Author

    Ejnioui, Abdel ; Ranganathan, Nagarajan

  • Author_Institution
    Electr. Eng. & Comput. Sci. Dept., Univ. of Central Florida, Orlando, FL, USA
  • Volume
    11
  • Issue
    1
  • fYear
    2003
  • Firstpage
    71
  • Lastpage
    78
  • Abstract
    Multi-FPGA (field-programmable gate arrays) systems are used as custom computing machines to solve compute-intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multiterminal nets in a multi-FPGA system that uses partial crossbars as interconnect structures. First, we model the multiterminal routing problem as a partitioned bin-packing problem and formulate it as an integer linear programming problem where the number of variables is exponential. A fast heuristic is applied to compute an upper bound on the routing solution. Then, a column generation technique is used to solve the linear relaxation of the initial master problem in order to obtain a lower bound on the routing solution. This is followed by an iterative branch-and-price procedure that attempts to find a routing solution somewhere between the two established bounds. In this regard, the proposed algorithm guarantees an exact-routing solution by searching a branch-and-price tree. Due to the tightness of the bounds, the branch-and-price tree is small resulting in shorter execution times. Experimental results are provided for different netlists and board configurations in order to demonstrate the algorithms performance. The obtained results show that the algorithm finds an exact routing solution in a very short time.
  • Keywords
    VLSI; bin packing; circuit layout CAD; circuit optimisation; field programmable gate arrays; high level synthesis; integer programming; integrated circuit layout; iterative methods; linear programming; logic partitioning; multiterminal networks; network routing; trees (mathematics); FPGA architecture; FPGA routing; branch-and-price tree searching; fast heuristic; integer linear programming problem; interconnect optimization; iterative branch-and-price procedure; layout synthesis; multiterminal net routing; multiterminal routing problem modelling; partial crossbar-based multi-FPGA systems; partial crossbars interconnect structures; partitioned bin-packing problem; partitioning tool; routing solution upper bound; Computer architecture; Costs; Delay; Field programmable gate arrays; Integer linear programming; Integrated circuit interconnections; Iterative algorithms; Prototypes; Routing; Upper bound;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2002.800523
  • Filename
    1191322