Title :
Low-power and area-efficient FIR filter implementation suitable for multiple taps
Author :
Kim, Kyung-Saeng ; Lee, Kwyro
Author_Institution :
Hynix Semicond. Inc., Seoul, South Korea
Abstract :
This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-/spl mu/m CMOS technology with three levels of metal. The chip that occupies 2.3/spl times/2.5 mm/sup 2/ of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V/sub dd/=3.3 V.
Keywords :
CMOS digital integrated circuits; FIR filters; VLSI; digital filters; low-power electronics; 0.6 micron; 16-tap macros; 20 MHz; 3.3 V; 32-tap FIR filter; 75 mW; CMOS digital filter; CMOS technology; VLSI; area-efficient FIR filter implementation; finite impulse response filter; low-power dissipation; power consumption reduction; separated shifting-accessing clock scheme; CMOS technology; Capacitance; Clocks; Digital filters; Energy consumption; Filtering; Finite impulse response filter; Frequency; Silicon; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2002.801570
