Title :
Alternative implementation of systolic recursive digital filters
Author_Institution :
Tokyo Inst. of Technol., Japan
fDate :
7/20/1989 12:00:00 AM
Abstract :
A new systolic array for the implementation of a recursive digital filter is presented. The operation-delay macro-component and the unit delay are the only elements composing the filter architecture. This architecture is fully pipelined and the output can be taken every cycle.
Keywords :
cellular arrays; digital filters; pipeline processing; recursive functions; filter architecture; operation-delay macro-component; pipelined; systolic array; systolic recursive digital filters; unit delay;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19890657
