• DocumentCode
    1171673
  • Title

    A methodology for the simultaneous design of supply and signal networks

  • Author

    Su, Haihua ; Hu, Jiang ; Sapatnekar, Sachin S. ; Nassif, Sani R.

  • Author_Institution
    IBM Corp., Austin, TX, USA
  • Volume
    23
  • Issue
    12
  • fYear
    2004
  • Firstpage
    1614
  • Lastpage
    1624
  • Abstract
    We present an early-stage global wire-design methodology that simultaneously considers the performance needs for both signal lines and power grids under congestion considerations. An iterative procedure is employed in which the global routing is performed according to a congestion map that includes the resource utilization of the power grid, followed by a step in which the power grid is adjusted to relax the congestion in crowded regions. This adjustment is in the form of wire removal in noncritical regions, followed by a wire-sizing step that overcomes the voltage noise after wire removal and a wire-width resizing that meets the maximum current-density constraint. Experimental results show that the overall routability can be significantly improved while the power-grid noise is maintained within both the voltage-drop and current-density constraints.
  • Keywords
    circuit layout CAD; circuit optimisation; current density; integrated circuit design; integrated circuit noise; iterative methods; network routing; circuit optimization; congestion map; current-density constraint; design automation; global routing; global wire-design methodology; iterative procedure; power distribution; power grids; power-grid noise; resource utilization; signal lines; signal networks; supply networks; voltage noise; voltage-drop constraints; wire removal; wire-width resizing; Design automation; Design optimization; Power distribution; Power grids; Resource management; Routing; Semiconductor device noise; Signal design; Voltage; Wires; 65; Circuit optimization; design automation; power distribution; routing; sensitivity;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2004.837728
  • Filename
    1362732