Generation of test patterns without prohibited pattern set

Author

Sikdar, Biplab K. ; Ganguly, Niloy ; Chaudhuri, P. Pal

Author_Institution

Dept. of Comput. Sci. & Technol., Bengal Eng. Coll., Howrah, India

Volume

23

Issue

12

fYear

2004

Firstpage

1650

Lastpage

1660

Abstract

This work reports the design of a fool proof on-chip test pattern generator (TPG) for very large scale integration circuits. The TPG is designed to generate pseudorandom test patterns without a given prohibited pattern set (PPS). It ensures desired pseudorandom quality of the generated test patterns and maintains fault coverage close to the figures achieved with a conventional maximal length linear feedback shift register/cellular automaton (CA)-based TPG. The theory of vector subspace generated by a CA (Chaudhuri, 1997) has provided the foundation of this design. The proposed TPG does not incur any additional cost for the avoidance of PPS.

Keywords

automatic test pattern generation; built-in self test; cellular automata; logic simulation; random number generation; shift registers; cellular automaton; linear feedback shift register; prohibited pattern set; pseudorandom test patterns; test pattern generation; vector subspace theory; very large scale integration circuits; Automata; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Linear feedback shift registers; Test pattern generators; Vectors; Very large scale integration; 65; CA; CA test pattern generator; CATPG; Cellular automata; TPG; prohibited patterns;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2004.837730

Filename

1362735