An efficient technique for exploring register file size in ASIP design

Performance estimation is a crucial operation which drives the design space exploration in an application-specific instruction set processor synthesis. With the increase in the level of integration, the design space has considerably expanded, which makes the simulation-driven techniques inadequate due to their slow speed. Alternatively, there are approaches which estimate performance by scheduling the application on the available processor resources without generating code. These are much more effective in exploring a large design space. The technique reported in this paper presents a scheduler-based approach for register file-size exploration. The performance is estimated by computing the number of spills for a particular register file size. The concept of register reuse chains is used for local register allocation, while live variable analysis done across the blocks is used to estimate global register needs. The technique is fast, accurate, retargetable, and does not require code generation. We have generated and validated execution-time estimates for selected benchmarks for a RISC (ARM7TDMI) and a VLIW (TM-1000) processor. Further, we have shown that this approach is much faster than simulator-based techniques.