A very-high-slew-rate CMOS operational amplifier

Author

Klinke, R. ; Hosticka, B.J. ; Pfleiderer, H.J.

Author_Institution

Fraunhofer Inst. for Microelectron. Circuits & Syst., Duisburg, West Germany

Volume

24

Issue

3

fYear

1989

fDate

6/1/1989 12:00:00 AM

Firstpage

744

Lastpage

746

Abstract

The amplifier uses a circuit to inject an extra bias current into a conventional source-coupled CMOS differential input stage in the presence of large differential input signals. This measure substantially increases the slew rate of an operational amplifier for a given quiescent current. The performance of the amplifier is compared to a conventional operational amplifier when used in a sample-and-hold circuit. The maximum operating clock frequency of the sample-and-hold increases from 290 kHz to 1 MHz with a hold capacitor of 1 nF. The amplifier has been fabricated in a 5-μm CMOS process and dissipates a static power of 7.5 mW

Keywords

CMOS integrated circuits; operational amplifiers; sample and hold circuits; 1 MHz; 5 micron; 7.5 mW; CMOS operational amplifier; bias current; clock frequency; differential input signals; quiescent current; sample-and-hold circuit; slew-rate; source-coupled CMOS differential input stage; Capacitance; Capacitors; Circuit noise; Current measurement; Differential amplifiers; Frequency response; Impedance; Operational amplifiers; Power dissipation; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.32035

Filename

32035