1-Gword/s pseudorandom word generator

Author

McFarland, William J. ; Springer, Kent H. ; Yen, Chu-Sun

Author_Institution

Hewlett-Packard Lab., Palo Alto, CA, USA

Volume

24

Issue

3

fYear

1989

fDate

6/1/1989 12:00:00 AM

Firstpage

747

Lastpage

751

Abstract

An integrated circuit that generates 16-bit pseudorandom words at up to 1 Gword/s is presented. The concept of a pseudorandom word sequence is introduced. The pseudorandom words shown have excellent properties for testing serial or parallel components and data links. If serialized, the words would form a pseudorandom bit sequence with a potential maximum serial bit rate of 16 Gb/s. The circuit was implemented in an advanced silicon bipolar process with an f _T of 10 GHz. The chip includes 16 output drivers, with adjustable amplitude and offset, capable of driving 25-Ω loads with 0.8-V swings and 400-ps rise times. Total chip dissipation is under 4 W on a 2-mm×2-mm die

Keywords

sequential circuits; shift registers; 16 bits; Si; amplitude; bipolar process; data links; offset; output drivers; parallel components; pseudorandom bit sequence; pseudorandom word generator; pseudorandom word sequence; rise times; serial bit rate; total chip dissipation; Bit rate; Circuit testing; Clocks; Driver circuits; Frequency; Gallium arsenide; Multiplexing; Optical fiber testing; Silicon; System testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.32036

Filename

32036