Title :
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode
Author :
Watanabe, Shigeyoshi ; Oowaki, Yukihito ; Itoh, Yasuo ; Sakui, Koji ; Numata, Kenji ; Fuse, Tsuneaki ; Kobayashi, Takayuki ; Tsuchida, Kenji ; Chiba, Masahiko ; Hara, Takahiko ; Ohta, Masako ; Horiguchi, Fumio ; Hieda, Katsuhiko ; Mitayama, A. ; Hamamoto,
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
6/1/1989 12:00:00 AM
Abstract :
A 5-V 4M-word×4-b dynamic RAM (random-access memory) with a 100-MHz serial read/write mode using 0.7-μm triple-tub CMOS technology is discussed. The RAM utilizes a recently developed STT (stacked trench capacitor) cell which achieved 37 fF in a small cell size of 1.7×3.6 μm2. The STD (sidewall transistor with double-doped drain) structure is used for PMOS-FETs to realize high-speed operation. To ensure MOSFET reliability, the 5-V external supply voltage is converted to a 4-V internal supply voltage by an on-chip voltage converter circuit. An on-chip interleaved circuit and double-input-buffer scheme is used to realize high-speed serial read/write operation. Using an external 5-V power supply, the RAM achieved a 100-MHz serial access cycle, and RAS access time is 70 ns. The typical active current is 120 mA at a 190-ns cycle time
Keywords :
CMOS integrated circuits; VLSI; integrated memory circuits; random-access storage; 0.7 micron; 100 MHz; 16 Mbit; 70 ns; CMOS DRAM chip; MOSFET reliability; PMOS-FETs; STD; access time; cell size; double-input-buffer scheme; on-chip interleaved circuit; on-chip voltage converter circuit; serial access cycle; serial read/write mode; sidewall transistor with double-doped drain; stacked trench capacitor; triple-tub CMOS technology; CMOS technology; Capacitance; Capacitors; Diodes; Fuses; Leakage current; MOSFET circuits; Random access memory; Read-write memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
