A 40-Mpixel/s bit block transfer graphics processor

Author

Sumi, Masahiko ; Tanaka, Shigeru ; Kai, Naoyuki ; Miyazawa, Yuichi ; Nagamatsu, Masato ; Minagawa, Tsutomu ; Nagashima, Ichiro ; Hamai, Tsuneo ; Mori, Junji ; Noguchi, Tatsuo

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

24

Issue

3

fYear

1989

fDate

6/1/1989 12:00:00 AM

Firstpage

830

Lastpage

835

Abstract

A man-machine-interface-oriented graphics processor featuring data transfer speed of over 40 picture/s and character-front bit-mapped speed of over 15000 characters/s in a 1024×768-pixel-resolution color-CRT (cathode-ray-tube) system is discussed. The high-speed operation was attained by a memory interleaving scheme. The detailed timing for the high-speed scheme and its compactness are shown, using an actually fabricated application board. The chip layout was accomplished with a standard-cell-based approach with 1.0-μm CMOS process

Keywords

CMOS integrated circuits; cathode-ray tube displays; computer graphic equipment; digital signal processing chips; 1.0 micron; CMOS process; application board; character-front bit-mapped speed; color-CRT; data transfer speed; man-machine-interface-oriented graphics processor; memory interleaving scheme; standard-cell-based approach; Cathode ray tubes; Color; Control systems; Displays; Graphics; Laboratories; Large scale integration; Magnetooptic recording; Timing; User interfaces;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.32046

Filename

32046