DocumentCode :
1172192
Title :
Novel dual bit tri-gate charge trapping memory devices
Author :
Specht, M. ; Kömmling, R. ; Hofmann, F. ; Klandzievski, V. ; Dreeskornfeld, L. ; Weber, W. ; Kretz, J. ; Landgraf, E. ; Schulz, T. ; Hartwich, J. ; Rösner, W. ; Städele, M. ; Luyken, R.J. ; Reisinger, H. ; Graham, A. ; Hartmann, E. ; Risch, L.
Author_Institution :
Infineon Technol., Munich, Germany
Volume :
25
Issue :
12
fYear :
2004
Firstpage :
810
Lastpage :
812
Abstract :
Dual bit operation of fabricated tri-gate nonvolatile memory devices with aggressively scaled oxide-nitride-oxide (ONO) dielectrics is presented for the first time. Compared to a planar cell, the proposed tri-gate device architecture offers higher readout currents and improved electrostatic gate control of the channel region yielding very good scalability of the devices. We have investigated devices with gate lengths in the range LG=100-220 nm and we focus on their write-erase, retention, and cycling characteristics.
Keywords :
charge injection; dielectric materials; readout electronics; semiconductor device manufacture; semiconductor storage; charge injection; charge-trapping memory; dual bit operation; electrostatic gate control; fabricated tri-gate nonvolatile memory devices; oxide-nitride-oxide dielectrics; readout currents; semiconductor device fabrication; tri-gate charge trapping memory devices; tri-gate transistor; Dielectric devices; Dry etching; Electrostatics; Fabrication; Lithography; Nonvolatile memory; Rapid thermal processing; Scalability; Semiconductor devices; Silicon; 65; Charge injection; charge-trapping memory; semiconductor device fabrication; tri-gate transistor;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/LED.2004.838621
Filename :
1362783
Link To Document :
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