CAM-based VLSI architectures for dynamic Huffman coding

Author

Liu, Liang-Ying ; Wang, Jhing-Fa ; Ruey-Jen Wang ; Lee, Jau-Yien

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

40

Issue

3

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

282

Lastpage

289

Abstract

The dynamic Huffman coding is a data compression technique, and famous for its flexibility. However, it has not been available for real-time applications because the adaption process is complex. In this paper, we proposed the architectures for dynamic Huffman coding. Both of the encoder and decoder are constructed by using the CAM-based memory modules. These memory modules parallelly perform the adaption, process so that the coding can be efficiently executed. The encoder with the code table containing 32 symbols has been implemented. The simulation results show that the encoder can yield a input throughput of 40 Mbps operating at 40 MHz with 50% compression ratio

Keywords

CMOS integrated circuits; Huffman codes; VLSI; content-addressable storage; decoding; encoding; integrated memory circuits; memory architecture; 40 MHz; 40 Mbit/s; CAM-based memory module; VLSI architectures; coding; compression ratio; data compression; decoder; dynamic Huffman coding; encoder; input throughput; simulation results; Bandwidth; CMOS technology; Circuits; Communication networks; DH-HEMTs; Decoding; Educational institutions; Huffman coding; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.320807

Filename

320807