A 2.5-V 14-bit ΣΔ CMOS SOI capacitive accelerometer

Author

Amini, Babak Vakili ; Ayazi, Farrokh

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

39

Issue

12

fYear

2004

Firstpage

2467

Lastpage

2476

Abstract

This paper presents a 2.5-V 14-bit fully differential ΣΔ interface circuit in 0.25-μm CMOS technology for a high-resolution silicon-on-insulator capacitive accelerometer fabricated using a simple CMOS-compatible stictionless process. The integrated circuit is based on programmable front-end back-end first-order ΣΔ architecture and provides a 1-bit pulse-width modulated digital output. Using correlated double sampling, the low-frequency noise is suppressed by 10 dB. Capacitive resolution is 22 aF at 75 Hz (resolution bandwidth = 1 Hz), equivalent to 110 μg with a dynamic range of 85 dB (14-bit resolution) and a sensitivity of 500 mV/g. The chip occupies 2 mm² and consumes 6 mW.

Keywords

CMOS integrated circuits; accelerometers; micromechanical devices; sigma-delta modulation; signal sampling; silicon-on-insulator; switched capacitor networks; 0.25 micron; 1 Hz; 14 bit; 2.5 V; 6 mW; 75 Hz; MEMS interface circuit; capacitive accelerometer; capacitive resolution; correlated double sampling; noise suppression; programmable switched-capacitor amplifier; sigma-delta CMOS; sigma-delta modulator; silicon-on-insulator; Accelerometers; CMOS process; CMOS technology; Digital integrated circuits; Digital modulation; Integrated circuit technology; Modulation coding; Pulse circuits; Silicon on insulator technology; Space vector pulse width modulation; 65; CDS; CMOS SOI capacitive accelerometers; MEMS interface circuit; correlated double sampling; programmable switched-capacitor amplifier; sigma-delta modulator;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.837025

Filename

1362857