Negative Differential Resistance Circuit Design and Memory Applications

Author

Chen, Shu-Lu ; Griffin, Peter B. ; Plummer, James D.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA

Volume

56

Issue

4

fYear

2009

fDate

4/1/2009 12:00:00 AM

Firstpage

634

Lastpage

640

Abstract

Based on a circuit point of view, a high-performance negative differential resistance (NDR) element is designed and a possible compact device implementation is presented. The NDR structure exhibits ultrahigh peak-to-valley current ratio and also high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology, as they rely on coupled transistor structures. A single-NDR element static-random-access-memory cell prototype with a compact size and high speed is proposed as an interesting application suitable for embedded memory.

Keywords

CMOS integrated circuits; embedded systems; integrated circuit design; CMOS technology; negative differential resistance circuit design; static-random-access-memory cell; ultrahigh peak-to-valley current ratio; CMOS technology; Character generation; Circuit synthesis; Circuit topology; Diodes; MOSFET circuits; Random access memory; Solid state circuits; Surface resistance; Tunneling; Metal–oxide–semiconductor field-effect transistor (MOSFET); NDR-based static random access memory (SRAM); negative differential resistance (NDR); peak-to-valley current ratio (PVCR);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2009.2014194

Filename

4787036