Title :
Sub-300-ps CBL circuits
Author :
Widemann, S.K. ; Chen, Tze-Chiang ; Chuang, Ching-Te ; Heuber, K. ; Wendel, D.F. ; Warnock, James ; Li, G.P. ; Chin, K. ; Ning, Tak H.
Author_Institution :
IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a ´free´ epi-base lateral p-n-p (cutoff frequency=300 MHz only), and deep trench isolation are discussed. Using 1.2- mu m design rules and a modified push-pull output stage, a gate delay (fan-in=3) of 278 ps was obtained at a DC current of 30 mu A/gate. The low power-delay product underlies the speed and power potential of CBL as an attractive practical approach to bipolar complementary transistor logic.<>
Keywords :
bipolar integrated circuits; integrated logic circuits; 1.2 micron; 278 ps; 30 muA; 300 MHz; DC current; bipolar complementary transistor logic; charge buffered logic circuits; cutoff frequency; deep trench isolation; design rules; double-poly self-alignment; fan-in; free epi base lateral p-n-p; gate delay; modified push-pull output stage; power-delay product; Buffer storage; Circuits; Cutoff frequency; Delay; Diodes; Isolation technology; Logic devices; MOSFETs; Power dissipation;
Journal_Title :
Electron Device Letters, IEEE
