A novel elevated MOSFET source/drain structure

Author

Orlowski, Marius ; Mazure, C. ; Noell, Matthew

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

12

Issue

11

fYear

1991

Firstpage

593

Lastpage

595

Abstract

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25- mu m level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics.<>

Keywords

insulated gate field effect transistors; 0.25 micron; 3.3 V.; MOSFET scaling; crystalline Si spacer; elevated MOSFET source/drain structure; high hot carrier injection tolerance; high impact ionization tolerance; low-doped Si spacer; performance; polycrystalline Si spacer; reliability; supply voltage; vertically layered elevated drain structure; Character generation; Crystallization; Degradation; Hot carrier injection; Hot carriers; Human computer interaction; Impact ionization; MOSFET circuits; Silicon; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.119208

Filename

119208