Congestion estimation for 3-D circuit architectures

Author

Cheng, Lerong ; Hung, William N N ; Yang, Guowu ; Song, Xiaoyu

Author_Institution

Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA

Volume

51

Issue

12

fYear

2004

Firstpage

655

Lastpage

659

Abstract

Three-dimensional (3-D) routing is an important step in deep submicrometer very large-scale integrated design. Given a 3-D grid graph and a set of two-terminal nets to be routed, we propose a probabilistic model to calculate the routing density (congestion) on each edge of the grid graph. The routing density provides a direct congestion estimation. Our experimental results demonstrate the effectiveness of the method on routing benchmarks.

Keywords

VLSI; estimation theory; graph theory; integrated circuit design; network routing; probability; 3D circuit architecture; 3D grid graph; 3D routing; congestion estimation; deep submicrometer VLSI; probabilistic method; probabilistic model; routing density; very large-scale integrated design; Application specific integrated circuits; Field programmable gate arrays; Integrated circuit interconnections; Integrated circuit technology; Joining processes; Multichip modules; Printed circuits; Process design; Routing; Very large scale integration; 65; Estimation; probabilistic methods; routing;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2004.838548

Filename

1362938