DocumentCode
1173667
Title
Analysis and implementation of practical, cost-effective networks on chips
Author
Lee, Se-Joong ; Lee, Kangmin ; Yoo, Hoi-Jun
Author_Institution
Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Volume
22
Issue
5
fYear
2005
Firstpage
422
Lastpage
433
Abstract
This article describes design issues in three NoCs (network on chip) that exploit star and mesh networks, with the objective of comparing area and energy costs. We present new solutions based on mesochronous communication and burst packet transactions.
Keywords
microprocessor chips; multiprocessor interconnection networks; parallel architectures; system-on-chip; telecommunication network topology; NoC design; burst packet transaction; cost-effective networks on chip; mesh network; mesochronous communication; microprocessor chip; multiprocessor interconnection network; parallel architecture; star network; system-on-chip; Clocks; Costs; Delay; Energy consumption; Frequency synchronization; Intelligent systems; Mesh networks; Network topology; Network-on-a-chip; Switches; Advanced technologies; Network connectivity chips; VLSI;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2005.103
Filename
1511974
Link To Document