DocumentCode
1173676
Title
Analysis of error recovery schemes for networks on chips
Author
Murali, Srinivasan ; Theocharides, Theocharis ; Vijaykrishnan, N. ; Irwin, Mary Jane ; Benini, Luca ; De Micheli, Giovanni
Author_Institution
Stanford Univ., CA, USA
Volume
22
Issue
5
fYear
2005
Firstpage
434
Lastpage
442
Abstract
In this article, we discuss design constraints to characterize efficient error recovery mechanisms for the NoC design environment. We explore error control mechanisms at the data link and network layers and present the schemes´ architectural details. We investigate the energy efficiency, error protection efficiency, and performance impact of various error recovery mechanisms.
Keywords
energy conservation; multiprocessor interconnection networks; parallel architectures; power consumption; system-on-chip; NoC design constraints; data link layer; energy efficiency; error protection efficiency; error recovery scheme; network layer; network on chip; system-on-chip; Communication system control; Crosstalk; Design automation; Error analysis; Error correction; Error correction codes; IEEE Press; Network-on-a-chip; Routing; Switches; I/O and Data Communications; Performance and Reliability;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2005.104
Filename
1511975
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