• DocumentCode
    1173783
  • Title

    An approach that will NoC your SoCs off!

  • Author

    Saleh, Res

  • Author_Institution
    Natural Sciences and Engineering Research Council of Canada, PMC-Sierra Inc., and University of British Columbia
  • Volume
    22
  • Issue
    5
  • fYear
    2005
  • Firstpage
    488
  • Lastpage
    488
  • Abstract
    New structured communication fabrics, called networks on chips (NoCs), have emerged for use in SoC designs. The basic concept is to communicate across the chip in the same way that messages are transmitted over the internet today. That is, put a packet-switching network on the chip and send messages back and forth between blocks. Designers have already resolved most of the issues in the Internet domain, so it´s just a matter of bringing that knowledge to the chip. Of course, NoC is not a panacea. It does seem appropriate for the multiprocessor SoC platforms that are homogeneous in nature, but the jury is still out on the value of NoC for chips with heterogeneous IP blocks.
  • Keywords
    IP blocks; Moore´s law; SoC design; interconnect delay; networks on chips; Councils; Design engineering; Network-on-a-chip; Testing; IP blocks; Moore´s law; SoC design; interconnect delay; networks on chips;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2005.101
  • Filename
    1511986