Logic partition for multiemitter two-level structures

The efficient use of high-speed logic modules depends on logic designs in which the fan numbers are kept small and the number of logic delays for critical signals held to a minimum. A logic partition technique is developed, based on the simple decomposition methods of Ashenhurst, which allows the efficient use of a multiemitter two-level logic (METLL) structure. where the logic performed at one level is controlled by the input applied to the other. As examples, the technique is applied to high-speed adders and an iterative multiplier.