DocumentCode :
1174159
Title :
Modeling of large-grain polysilicon formation under retardation effect of SPC
Author :
Cheng, C.F. ; Leung, T.C. ; Poon, M.C. ; Kok, C.W. ; Chan, Mansun
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Volume :
51
Issue :
12
fYear :
2004
Firstpage :
2205
Lastpage :
2210
Abstract :
This paper details the study of the mechanism of large-grain polysilicon layer formations using metal-induced lateral crystallization (MILC). A model is proposed to predict the growth rate of MILC under the retardation effect of solid-phase crystallization (SPC) at different annealing conditions. The model has been extensively validated by experimental data. This paper will show that the SPC exists as a counter-effect to retard the MILC and degrade the superiority of the polysilicon layer. The model has been used to predict the MILC rate of large-grain polysilicon grown by a pulsed-annealing technique that suppresses the undesirable SPC effect. The model prediction agrees well with the experimental results.
Keywords :
annealing; crystal growth; crystallisation; thin film transistors; annealing conditions; growth rate prediction; large-grain polysilicon formation; metal-induced lateral crystallization; polysilicon layer; pulsed-annealing technique; retardation effect; solid-phase crystallization; thermal annealing; thin-film transistor; Annealing; Atomic layer deposition; Crystallization; Grain size; Microwave integrated circuits; Nickel; Predictive models; Senior members; Temperature; Thin film transistors; 65; Crystallization; TFT; large-grain; polysilicon; thermal annealing; thin-film transistor;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2004.838323
Filename :
1362989
Link To Document :
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