Memory-efficient Radix-2 FFT processor using CORDIC algorithm

In this paper, a new memory-efficient architecture is presented for Radix-2 FFT processor using CORDIC algorithm. In the proposed memory-efficient FFT processor, an address decoding scheme is used to generate real time angles for the pipelined Radix-2 butterfly. This eliminates the need for storing twiddle factors and angles. This also results in significant area savings with no negative impact on performance. An efficient addressing scheme is implemented to realize the “in-place” Serial-in and Serial-out memory accessing. Here, the synthesis results match the theoretical analysis and it can be observed that a significant reduction can be achieved in total memory logic.