Title :
Behavioral to structural translation in a bit-serial silicon compiler
Author :
Hartley, Richard I. ; Jasica, Jeffrey R.
Author_Institution :
Gen. Electr. Res. & Dev. Center, Schenectady, NY, USA
fDate :
8/1/1988 12:00:00 AM
Abstract :
After a brief discussion of previous work in the field of behavioral-to-structural translation, the bit-serial architecture which is the target of the bit-serial compiler is discussed. The bit-serial language (BSL) is then defined, and the details of the behavioral-to-structural translation are given
Keywords :
circuit layout CAD; behavioral-to-structural translation; bit-serial architecture; bit-serial language; bit-serial silicon compiler; Arithmetic; Circuits; Computer architecture; Delay; Flow graphs; Linear programming; Scheduling algorithm; Signal processing algorithms; Silicon compiler; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
