Design of constant delay logic style for high speed adder

Low power microelectronics has become more intense and low power VLSI systems having emerged as greatly in demand. For increasing number of portable applications require small area low power high throughput. High speed high throughput, small silicon area and at the same time low power consumption is the motivation behind this. This paper presents an effective approach of constant delay (CD) logic style targeting at high-speed applications. Characteristic of this CD logic style without concern of the logic type makes it suitable in implementing complicated logic expressions such as addition. A “timing window” technique is also proposed to reduce the amount of excessive power dissipation in the CD approach. The concept is validated through the simulation of 32-bit Carry look ahead adder with Constant delay logic style using Tanner EDA v13.0.