• DocumentCode
    1175167
  • Title

    CMOS output buffers for megabit DRAMs

  • Author

    Pribyl, W. ; Harter, J. ; Reczek, W. ; Sommer, D. ; Hausele, H.

  • Author_Institution
    Siemens AG, Munich, West Germany
  • Volume
    23
  • Issue
    3
  • fYear
    1988
  • fDate
    6/1/1988 12:00:00 AM
  • Firstpage
    816
  • Lastpage
    819
  • Abstract
    Output buffers for CMOS DRAMs are discussed and associated reliability risks and circuit design problems are shown. Concepts using true CMOS circuitry for output buffers are presented. Measurement results prove the feasibility of latch-up-free CMOS output structures, which have been implemented on a 4-Mb DRAM and use significantly less area than boosted NMOS concepts.<>
  • Keywords
    CMOS integrated circuits; circuit reliability; integrated memory circuits; random-access storage; 1 to 4 Mbit; CMOS output buffers; circuit design; dynamic RAM; latchup free output structures; memory circuits; reliability; Breakdown voltage; CMOS logic circuits; Circuit synthesis; Clocks; Logic design; MOS devices; Pins; Random access memory; Switches; Switching circuits;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.322
  • Filename
    322
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1175167