Automatic IC layout: The model and technology

A procedure to obtain the topological data necessary for a proper layout of a monolithic integrated circuit in planar technology is presented. The first section gives a short summary of the graph theoretic formulation of the layout problem. The "extended potential graph" is defined, of which planarity is necessary and sufficient for the existence of a layout satisfying a number of requirements. The second section extensively describes technological possibilities to planarize this graph. After the planarization of the potential graph, some additional data is needed for diffusions that are no longer represented in the modified potential graph. These data can be supplied by an optimization procedure described in the third section. Finally an example illustrates the contents of this paper and some concluding remarks give the relation of this procedure to existing literature in this field.