VLSI implementation of efficient split radix FFT based on distributed arithmetic

Fast Fourier Transform (FFT) is a very common operation used for various signal processing units. Many efficient algorithms are being designed to improve the architecture of FFT. Among the different algorithms, split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithm. The performance in terms of throughput of the processor is limited by the multiplication. Therefore multiplier is optimized to make the input to output delay as short as possible. Distributed arithmetic (DA) is one of the most used techniques in implementing multiplier-less architectures of many digital systems. In this paper a Split Radix FFT without the use of multiplier is designed. All the complex multiplications are done by using Distributed Arithmetic (DA) technique. For faster calculation parallel prefix adder is used. These algorithms reduces overall arithmetic operations in FFT, but increases the number of operations and complexity of each butterfly. In Split Radix FFT, mixed-radix approach helps to achieve low number of multiplications and additions. The advantage of DA is its efficiency of mechanization. A method is incorporated to overcome the overflow problem introduced by DA method.