TCAD simulation for low power UTBB FDSOI CMOS device

Author

Sharma, Ritu ; Baishya, S.

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol. Silchar, Silchar, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

4

Abstract

In this work a UTBB FDSOI model has been proposed by which leakage current is drastically reduced. Therefore it gives us freedom to scale down the device. Various comments on Sub-threshold slope (SS) and threshold voltage have been made. Effect of Buried Oxide (BOX) and Channel length variation has been described in terms of on-state current, off-state current, threshold voltage and SS. AC analysis of CMOS device has also been done by simulating the basic capacitance of proposed device. This model is highly appreciated for low power while using with multi threshold voltage.

Keywords

CMOS integrated circuits; buried layers; integrated circuit modelling; leakage currents; low-power electronics; TCAD simulation; buried oxide; channel length variation; leakage current reduction; low power UTBB FDSOI CMOS device; subthreshold slope; threshold voltage; CMOS integrated circuits; Capacitance; Logic gates; MOS devices; Semiconductor device modeling; Substrates; Threshold voltage; Channel Length; Fully Depleted (FD); Silicon on Insulator (SOI); Simulation; Sub-threshold slope; Threshold Voltage; Ultra Thin Body and BOX (UTBB);

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on

Conference_Location

Coimbatore

Type

conf

DOI

10.1109/ICGCCEE.2014.6922240

Filename

6922240