Design of low power shift register using activity-driven optimized clock gating and run-time power gating

This paper presents the implementation of a Four bit Serial Input Serial Output (SISO) Shift Register using combination of Activity-Driven Optimized Clock-gating (ADOC) scheme and Run Time Power Gating (RTPG). We have proposed Activity-Driven Fine-Grained CG and RTPG integration. First, we introduce an Activity-Driven Optimized Clock-Gating scheme to improve traditional XOR-based CG. It chooses only a subset of Flip-Flops to be gated selectively, then we introduce RTPG which is applied to each and every Flip Flop. The clock enable signal generated by ADOC scheme is used as the sleep signal to all the PG cells. The analysis is carried out using Tanner EDA-Industry Standard EDA design environment using 250nm technology. The simulation results show that the SISO Shift Register with ADOC & RTPG technique is 72.03% more efficient than the SISO Shift Register.