DocumentCode
117566
Title
Towards MuGFETs: A power reduction perspective
Author
Sushmitha, A. ; Narthanaa, K. ; Aravindan, I. ; Ajay Kumar, A.S. ; Sundari, B. Bala Tripura
Author_Institution
Dept. of Electron. & Commun. Eng., Amrita Vishwa Vidyapeetham, Coimbatore, India
fYear
2014
fDate
6-8 March 2014
Firstpage
1
Lastpage
6
Abstract
The progress towards making efficient chips, in terms of area, speed and power continues to remain a major concern of every silicon industry. The various effects that become prominent at nanometer level hinders this progress. This is a paper that looks into: scaling, its effects (short-channel effects, as it is called) and compares scaled single gate and scaled multiple gate FETs on important properties. The use of scaled multiple gate MOSFETs (MuGFETs) ensures better gate control and alpha-power model demonstrates reduction in time delay in MuGFETs, than in scaled single gate FETs. This shows that the short-channel effects are overcome by scaled MuGFETs, thereby not only facilitating higher packaging density, but also reducing power consumption and at the same time improving switching performance.
Keywords
MOSFET; delay circuits; semiconductor device packaging; MuGFET; alpha-power model; gate control; packaging density; power reduction perspective; scaled multiple gate FET; scaled multiple gate MOSFET; scaled single gate FET; scaling; short-channel effects; time delay; Logic gates; MOSFET; Power demand; Power dissipation; Threshold voltage; Power dissipation; multiple gate FETs; scaling; short channel effects; transistor leakage;
fLanguage
English
Publisher
ieee
Conference_Titel
Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on
Conference_Location
Coimbatore
Type
conf
DOI
10.1109/ICGCCEE.2014.6922242
Filename
6922242
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