VLSI design of low power SRAM architectures for FPGAs

Author

Kaushik, Chakka Sri Harsha ; Vanjarlapati, Rajiv Reddy ; Krishna, Varada Murali ; Gautam, Tadvarthi ; Elamaran, V.

Author_Institution

Dept. of ECE, SASTRA Univ., Thanjavur, India

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

4

Abstract

SRAM cell, a semi-conductor memory, is majorly used to store/retrieve time independent data. SRAM cells of various configurations with proper understanding of their functioning are mentioned in this study. Typically, an SRAM cell uses six MOSFETS while various architectures for the cells are also available with the number of transistors ranging from 4 to 12 and more. The architectures are different from each other with respect to parameters such as data retention stability, area, power dissipation, feature size. With the size of designs scaling down drastically, the power consumption is tending to be an issue and this study involves difference design architectures of low power SRAM cells. Electronic computer aided design software tools like Digital Schematic editor and the Microwind layout editor are used to obtain the required simulation results.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; field programmable gate arrays; integrated circuit design; low-power electronics; FPGA; MOSFET; VLSI design; data retention stability; feature size; integrated circuit area; low power SRAM architecture; power dissipation; semiconductor memory; Computer architecture; Field programmable gate arrays; Layout; SRAM cells; Stability analysis; Transistors; CMOS; FPGA; Microwind; PROM; Pseudo-nMOS; SRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on

Conference_Location

Coimbatore

Type

conf

DOI

10.1109/ICGCCEE.2014.6922244

Filename

6922244