Title :
Exponentially tapered H-tree clock distribution networks
Author :
El-Moursy, Magdy A. ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Rochester, NY, USA
Abstract :
Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%.
Keywords :
clocks; integrated circuit interconnections; integrated circuit noise; trees (mathematics); H-tree clock network; clock distribution network; dynamic power dissipation; inductive noise; propagation delay; signal transition time; signal waveform; tapered interconnect; Acoustic reflection; CMOS integrated circuits; Capacitance; Clocks; Integrated circuit interconnections; Integrated circuit noise; Noise reduction; Power dissipation; Propagation delay; Semiconductor device noise; Clock distribution network; H-trees; inductive noise; power dissipation; tapered interconnect;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2005.853602
