Title :
Design-for-testability for embedded delay-locked loops
Author :
Egan, Tom ; Mourad, Samiha
Author_Institution :
Dept. of Electr. Eng., Santa Clara Univ., CA, USA
Abstract :
This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the loop´s response to a step in phase. The concept of test construct (TC) gain is introduced as a means of improving detectability. The benefit of the testing approach is demonstrated by injecting defects into the DLL and detecting them through the TC at the observation point.
Keywords :
delay lock loops; design for testability; embedded systems; field programmable gate arrays; mixed analogue-digital integrated circuits; step response; system-on-chip; DLL; SoC; TC; application specific integrated circuit; control voltage; delay locked loops; design for testability; field-programmable gate array; step response; system-on-chip; test construct; Application specific integrated circuits; Circuit testing; Delay; Field programmable analog arrays; Field programmable gate arrays; Integrated circuit testing; Phase measurement; System testing; System-on-a-chip; Voltage control; Delay-locked loop (DLL); design for testability (DFT); embedded; step response; system-on-chip (SoC);
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2005.853622
