InvMixColumn decomposition and multilevel resource sharing in AES implementations

Hardware implementations of cryptography face increasingly more stringent demands for lower cost and greater computational power. In order to meet those demands, more efficient approaches to implementations are needed. This paper presents detailed studies of MixColumn and InvMixColumn operations used in Advanced Encryption Standard that aim at their hardware implementations in constrained environments. Our studies are supported by mathematical analysis of both transformations and lead to efficient serial and parallel decompositions. Furthermore, deeper resource sharing is demonstrated at word-, byte- and bit-level. All derived architectures are evaluated using popular low-cost field-programmable gate arrays. Application of proposed methods resulted in reduction of reconfigurable logic area of the complete cipher by up to 20%.