Analysis of thermal noise and noise reduction in CMOS device

Advanced CMOS technology assures CMOS device as a good choice for physical realization of RF applications. But as scaling progresses, noise and short channel effect start to deteriorate the device performance, thus increasing the power dissipation. This work focuses on the analysis of thermal noise by varying the gate resistance and frequency. Equivalent noise voltage is calculated for various extracted gate resistance and the effect of distributed gate resistance due to wider channel MOS is analyzed. Thermal noise is reduced using multifinger gate structure when compared to conventional nMOS. A complete small signal equivalent of nMOS along with augmented equivalent noise models is discussed.