Power reduction in network on chip links

Network on chips structure makes a fitting replacement for system on chip designs in designs incorporating large number of processing cores. In network on the major source of power dissipation is the network on chip links. If compared the power ratio between the network on chip links and router links are more power hungry than router. The dynamic power dissipation in links is major contributor to the power consumption in network on chip. This is due to the self switching and the second factor is cross coupling capacitance. In the proposed encoding technique the first self switching is reduce by checking the switching transition and then the coupling between the links is checked and ensured that the power consumption is reduced. This encoding technique is incorporated with the wormhole routed network. The end to end scheme incorporating the encoding technique to reduce power in the wormhole routed network on chip. The encoder and decoder of the proposed scheme with wormhole router are described in the RTL level in verilog HDL.