An integrated 16-channel CMOS time to digital converter

Author

Ljuslin, C. ; Christiansen, J. ; Marchioro, A. ; Klingsheim, O.

Author_Institution

CERN, Geneva, Switzerland

Volume

41

Issue

4

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

1104

Lastpage

1108

Abstract

An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 experiment at CERN has been developed in a 1 μm CMOS technology. The resolution is 156ns and the total time history is 204.8 ms. Buffering of up to 128 hits is done in on-chip FIFOs. The chip area is 25 mm². The vernier circuit consists of a 16-tap voltage-controlled delay chain controlled by a Delay Locked Loop (DLL). Read out is possible at 40 MHz. JTAG/IEEE 1149.1 protocol has been incorporated to allow in-site testing of the chip. The JTAG data path is also used to access internal control and status registers

Keywords

CMOS integrated circuits; analogue-digital conversion; delay circuits; detector circuits; integrated circuit testing; nuclear electronics; 1 mum; 16-tap voltage-controlled delay chain; 204.8 ms; 40 MHz; CMOS technology; JTAG data path; JTAG/IEEE 1149.1 protocol; NA48 experiment; delay locked loop; in-site testing; integrated 16-channel CMOS time to digital converter; internal control; on-chip FIFOs; status registers; vernier circuit; CMOS technology; Circuits; Clocks; Delay effects; Flip-flops; Inverters; Semiconductor device measurement; Spatial resolution; Time measurement; Timing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.322866

Filename

322866