Performance of non-delay-line constant-fraction discriminator timing circuits

The delay line in the constant-fraction discriminator (CFD) can be replaced with circuit networks to permit monolithic fabrication. The previously reported non-delay-line CFD utilizing a single-pole highpass filter is reviewed, followed by a presentation of non-delay-line circuits utilizing Gaussian lowpass filters. Circuit response for non-delay-line CFDs utilizing single-pole highpass or single-pole lowpass filters is shown to be equivalent. However, timing-signal underdrive and zero-crossing slope are increased and timing jitter reduced when higher-order lowpass filters are used. Comparisons of non-delay-line and delay-line CFD circuit timing performance are presented for lowpass-filtered step inputs representative of scintillation detector signals. Timing resolution of non-delay-line and delay-line CFDs is compared for BGO/photomultiplier scintillation detector applications. Monte Carlo simulations indicate that comparable timing resolution is available with proper selection of non-delay-line CFD filter time-constants. A fully-monolithic CMOS, non-delay-line CFD was fabricated to experimentally validate timing resolution. The measured timing resolution of 3.26 ns FWHM and 6.5 ns FWTM is in good agreement with measured resolution of 3.30 ns FWHM and 6.4 ns FWTM for a standard delay-line CFD circuit