A 64-ch Time Memory Cell module with a DSP and a VME interface

Author

Arai, Yasuo ; Ikeno, Masahiro

Author_Institution

KEK, Nat. Lab. for High Energy Phys., Ibaraki, Japan

Volume

41

Issue

4

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

1187

Lastpage

1191

Abstract

A new 64-channel Time Memory Cell (TMC) module has been developed for high-rate wire-chamber applications. A combination of the TMC chip and associated FIFO memories digitize and store input signals at 1 nsec/bit resolution for a period of 64 μsec. To handle the large data size, a digital signal processor (DSP56002) is implemented in the module. The size of the module is 9U×400 mm Euroboard size, and has a VME interface using the P1 and P2 connectors. The P3 connector has been assigned for the output of trigger signals

Keywords

CMOS integrated circuits; analogue-digital conversion; data acquisition; detector circuits; digital signal processing chips; nuclear electronics; physics computing; system buses; 64 mus; 64-channel; DSP56002; FIFO memories; P1 connector; P2 connector; P3 connector; Time Memory Cell; VME interface; digital signal processor; wire chamber readout; CAMAC; Connectors; Digital signal processing; Digital signal processing chips; Digital signal processors; Laboratories; Random access memory; Read-write memory; Signal resolution; Timing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.322881

Filename

322881