DocumentCode :
1177236
Title :
Performance optimization of critical nets through active shielding
Author :
Kaul, Himanshu ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
Electr. Eng. & Comput. Sci. Dept., Univ. of Michigan, Ann Arbor, MI, USA
Volume :
51
Issue :
12
fYear :
2004
Firstpage :
2417
Lastpage :
2435
Abstract :
We propose the concept of active shields-shields that switch concurrently with a signal wire of interest. Active shields aid signal transitions through the coupling between the signal wire and shields. For RC dominated wires, the active shields switch in the same phase as the signal wire since capacitive coupling is the dominant coupling mechanism. For wires with dominant inductive coupling, active shields switch in the opposite phase of the signal wire. We show that under fixed area and input capacitance constraints, in-phase active shielding outperforms traditional (passive) shielding and wire sizing/spacing techniques for minimizing delays and transition times on RC-dominated wires. For RLC wires, we demonstrate a region of feasibility (in terms of signal wire widths) for which opposite-phase active shielding outperforms the passive shielding technique. Opposite-phase active shielding suppresses ringing behavior to a greater degree than passive shields, providing similar performance to differential signaling while maintaining the simplicity of single ended signaling. The benefits of opposite-phase active shielding as compared to passive shielding are shown in the context of various clock net optimizations where reductions in ringing behavior (up to 4.5X) and transition times (up to 40% reduction) are achieved.
Keywords :
RC circuits; RLC circuits; capacitance; circuit optimisation; coupled circuits; electromagnetic shielding; inductance; integrated circuit interconnections; RC dominated wires; RLC wires; capacitive coupling; clock net optimizations; critical nets; differential signaling; in-phase active shielding; inductive coupling; on-chip interconnects; opposite-phase active shielding; passive shielding; ringing behavior suppression; signal transitions; signal wire; single ended signalling; wire sizing technique; wire spacing technique; CMOS technology; Capacitance; Clocks; Degradation; Delay; Frequency; Inductance; Optimization; Switches; Wire; 65; Capacitive coupling; inductive coupling; on-chip interconnects; shields;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2004.838247
Filename :
1364113
Link To Document :
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