A novel interleaver design for multimode communication in WLAN

This paper provides a novel multi mode interleaver which satisfies all the modulation schemes used in 802.16e. The proposed model is finite state machine based address generation with efficient use of FPGA memory block for storing the read and write address. In terms of maximum operating frequency finite state machine based address generation performs better as compared to the existing technique. Proposed design supports computation of interleaver address dynamically.