A bit-serial first-level calorimeter trigger for an LHC detector

A preliminary design of a compact first-level calorimeter trigger, implemented as a farm of local bit-serial systolic arrays, is presented. The bit-serial data representation allows higher processing rates and more compact designs than are possible when using parallel data. More functionality can be incorporated into the Application Specific Integrated Circuits (ASICs) that serve as the main processing elements. The trigger processor seeks local energy clusters, evaluates isolation criteria within the electromagnetic calorimeter and leakage into the hadron calorimeter in order to detect electrons. It uses cluster finding algorithms to identify jets and missing transverse energy to estimate neutrino energies. The processor output serves as decision support for the central first-level trigger and delivers region-of-interest positions to the second-level trigger. In its present form the trigger processor design relies on optical fibers to deliver the input data from the front-end modules and multi-chip modules (MCMs) to harbor the processing ASICs. The fact that the main part of the trigger processor can fit into one or two large crates suggests that the design is not limited by size nor is it strictly limited by cost but can be expanded to accommodate extended algorithms if these are found necessary. Extensive physics simulations will explore these possibilities