Hetero-gate-dielectric gate-drain underlap nanoscale TFET with a δp+ Si1−xGex layer at source-channel tunnel junction

Tunnel Field Effect Transistors (TFETs) have developed as promising devices for low power applications owing to their ability to sustain the effects of scaling. Sub-kT/q Subthreshold Swing (SS), lower off currents and negligible Short Channel Effects present them as suitable alternatives to MOSFETs. This work presents for the first time a hetero-gate-dielectric gate-drain underlap TFET with a δp⁺ Silicon Germanium layer at source-channel junction. The source, underlap and drain regions are overlapped by dielectrics with an objective to minimize the ambipolar current. An extremely impressive point SS of 22.44 mV/dec is obtained for Ge-mole fraction equal to 0.9 of the Si_1-xGe_x layer. Ratios of on and off currents greater than 10⁷ are achieved with acceptable gate threshold voltages.