HDL based implementation of N×N bit-serial multiplier

Author

Akhter, Shameem ; Chaturvedi, Sushil

Author_Institution

Dept. of Electron. & Commun. Eng., Jaypee Inst. of Inf. Technol., Noida, India

fYear

2014

fDate

20-21 Feb. 2014

Firstpage

470

Lastpage

474

Abstract

The paper proposes a systematic design methodology for bit-serial multiplication. The proposed approach is a modified method for performing traditional multiplication. This paper presents a general technique for N×N bit-serial multiplication used in signal processing. HDL implementation and simulation of 4×4 bit-serial multiplier is discussed. Synthesis is performed using Xilinx ISE with Virtex-4 ML402 FPGA board.

Keywords

field programmable gate arrays; hardware description languages; logic design; multiplying circuits; signal processing; 4x4 bit-serial multiplier simulation; HDL based implementation; N×N bit-serial multiplier; NxN bit-serial multiplication; Virtex-4 ML402 FPGA board; Xilinx ISE; signal processing; systematic design methodology; word length 4 bit; Adders; Clocks; Field programmable gate arrays; Flip-flops; Hardware design languages; Signal processing; Very large scale integration; Binary multiplication; FPGA; HDL; Parallel multiplier; Partial product; Serial bit multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing and Integrated Networks (SPIN), 2014 International Conference on

Conference_Location

Noida

Print_ISBN

978-1-4799-2865-1

Type

conf

DOI

10.1109/SPIN.2014.6776999

Filename

6776999