Topological generation and analysis of voltage multiplier circuits

Author

Lin, P.M. ; Chua, Leon O.

Volume

24

Issue

10

fYear

1977

fDate

10/1/1977 12:00:00 AM

Firstpage

517

Lastpage

530

Abstract

Voltage multipliers are used for transformerless conversion of an ac input voltage $\\upsilon _i(t)= E \\sin \\omega t$ into a dc output voltage $V_{out} = nE$ , where $n \\geq 2$ . This paper investigates the topological properties of voltage multiplier circuits and presents a unified approach for generating new voltage-multiplier circuit structures. In particular, an algorithm is presented for generating $n$ -fold voltage multipliers with $n$ capacitors and $n$ diodes. A theorem is presented for finding the dc capacitor voltages by inspection when no load current is drawn. For the case with load, explicit formulas for the output de voltage and the output resistance are given. Using the algorithm developed in this paper, three new voltage quadrupler circuits are generated and shown to have an output resistance only one-half of the conventional ladder quadrupler circuit.

Keywords

Network topology; Nonlinear networks; Nonlinear networks, time-varying; Voltage multipliers; Capacitors; Circuits; Diodes; Inspection; Joining processes; Power supplies; Rectifiers; TV; Virtual manufacturing; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/TCS.1977.1084273

Filename

1084273