A novel flexible baseband processor architecture framework

In recent years of development in wireless communication many baseband processors been proposed in various fields in order to propel the demand of high performance, less effective area, this changes according to the need of future developments. This paper presents an efficient processor architecture framework with respect to power consumption and area. The proposed framework can accommodate basic demands of extensive modulation schemes with reconfigurable feature. The framework of this baseband processor state 36% less area compared to normal states of architecture which results in 78% of area efficiency. This defines new ways of low power states and purposefully fulfills the need of performance with average higher throughput over time with less power consumption.