A novel DFAL based frequency divider

With the increased interest in low power digital devices operating at low frequencies, the demand for high performance adiabatic logic circuits is on the rise. A frequency divider is extensively used for frequency synthesis in transceivers, and Phase Locked Loops (PLL) circuits. This paper proposes a novel diode free adiabatic logic (DFAL) based frequency divider for low power applications. The proposed circuit eliminates the use of diodes in charging and discharging paths to lower the power consumption and amplitude degradation. The functionality of the proposed circuit is verified and compared with the two-phase clocked adiabatic static CMOS logic (2PASCL) based and conventional CMOS frequency divider. All the simulations are performed in Tanner EDA using 180nm CMOS technology parameters. The simulation result shows that the proposed DFAL frequency divider outperforms the 2PASCL divider.