Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

Author

Nii, Koji ; Tsukamoto, Yasumasa ; Yabuuchi, Makoto ; Masuda, Yasuhiro ; Imaoka, Susumu ; Usui, Keiichi ; Ohbayashi, Shigeki ; Makino, Hiroshi ; Shinohara, Hirofumi

Author_Institution

Renesas Technol. Corp., Itami

Volume

44

Issue

3

fYear

2009

fDate

3/1/2009 12:00:00 AM

Firstpage

977

Lastpage

986

Abstract

We propose an access scheme for a synchronous dual- port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit- line access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 mum² 8T-DP-cell for which the cell size is only 1.44 times larger than a 6T-single-port (SP)- cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm², which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

Keywords

CMOS memory circuits; SRAM chips; 8T-DP-cell area; CMOS technology; bit-density; cell stability; priority row decoder circuit; shifted bit-line access scheme; size 65 nm; small drive-NMOS transistor; synchronous dual-port SRAM; CMOS technology; Circuit stability; Clocks; Decoding; Frequency; Low voltage; Multicore processing; Random access memory; SRAM chips; System-on-a-chip; 65 nm; CMOS; dual-port; embedded SRAM; high density; low power; low voltage; memory; stability; two-port; variability;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2013766

Filename

4787570