DocumentCode :
1178554
Title :
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
Author :
Wang, Chang-Tzu ; Ker, Ming-Dou
Author_Institution :
Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu
Volume :
44
Issue :
3
fYear :
2009
fDate :
3/1/2009 12:00:00 AM
Firstpage :
956
Lastpage :
964
Abstract :
An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 mum 21 mum.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; leakage currents; nanoelectronics; power integrated circuits; thyristor circuits; SCR device; current 96 nA; electrostatic discharge; nanoscale CMOS technology; power-rail ESD clamp circuit design; size 65 nm; temperature 293 K to 298 K; ultra-low standby leakage current; voltage 1 V; voltage 325 V; voltage 7 kV; CMOS process; CMOS technology; Clamps; Electrostatic discharge; Leak detection; Leakage current; MOS capacitors; MOSFET circuits; Semiconductor device modeling; Thyristors; Electrostatic discharge (ESD); gate leakage; power-rail ESD clamp circuit; silicon controlled rectifier (SCR);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2008.2012372
Filename :
4787573
Link To Document :
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